| Code: |
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module lab2( byte1, byte2, carryin, out ); input [3:0] byte1, byte2; input carryin; output [3:0] out; wire [4:0] carry, gener, prop; wire [100:0] temp; integer k; for( k = 0; k < 4; k = k + 1 ) begin and ( gener[k], byte1[k], byte2[k] ); xor ( prop[1], byte1[1], byte2[1] ); end endmodule |
I don't know why this cannot be compile on altera quatras II. It gives me syntax errors at for, begin, and, xor, end lines.
Can anyone give me suggestions on how to fix the syntax errors on this code?
