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Programming in Verilog HDL





NewGuyinTown
Code:

module lab2( byte1, byte2, carryin, out );
input [3:0] byte1, byte2;
input carryin;
output [3:0] out;
wire [4:0] carry, gener, prop;
wire [100:0] temp;

integer k;
for( k = 0; k < 4; k = k + 1 )
begin
      and ( gener[k], byte1[k], byte2[k] );
      xor ( prop[1], byte1[1], byte2[1] );
end

endmodule


I don't know why this cannot be compile on altera quatras II. It gives me syntax errors at for, begin, and, xor, end lines.

Can anyone give me suggestions on how to fix the syntax errors on this code?
deepak
You should first import IEEE packages, I dont remember exactly VHDL right now, but pacakges are must like inculdes in C++
NewGuyinTown
I don't know what are the package names nor the statement that does this.

I'm not sure if this is revalant or not:

I am writing it on a .v file, not a .vhd file. (I would assume .v is a lower level language in comparison with .vhd similar to .c in comparison with .cpp)
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